The present invention relates to electrochemical processing of workpieces, and particularly for processes, apparatus and chemical solutions for depositing metals on microelectronic and micromechanical workpieces.
In the fabrication of microelectronic devices, application of one or more metallization layers is often an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, such as read/write heads, but it is more often used to interconnect components formed on a workpiece, such as a semiconductor workpiece. For example, such structures are used to interconnect the devices of an integrated circuit.
A basic understanding of certain terms used herein will assist the reader in understanding the disclosed subject matter. To this end, basic definitions of certain terms, as used in the present disclosure, are set forth below.
Single Metallization Level is defined as a composite level of a workpiece that is exterior to the substrate. The composite level comprises one or more metal structures.
Substrate is defined as a base layer of material over which one or more metallization levels are disposed. The substrate may be, for example, a semiconductor, a ceramic, etc.
Workpiece is defined as an object that at least comprises a substrate, and may include further layers of material or manufactured components, such as one or more metallization levels, disposed on the substrate. The workpiece may be, for example, a semiconductor wafer, a micromechanical device, or other device.
An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor. Devices which may be formed within the semiconductor include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
Delays in propagation of electrical signals between devices on a single die limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
For each interconnect path, signal propagation delay may be characterized by a time delay xcfx84. See E. H. Stevens, Interconnect Technology, QMC, Inc., Jul. 1993. An approximate expression for the time delay, xcfx84, as it relates to the transmission of a signal between transistors on an integrated circuit is given below.
xcfx84=RC[1+(VSAT//RISAT)]
In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path and ISAT and VSAT are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, xcfx81, of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, Ke, of the dielectric material. A small value of xcfx84 requires that the interconnect line carry a current density sufficiently large to make the ratio VSAT//RISAT small. It follows therefore, that a low-xcfx81 conductor which can carry a high current density and a low-Ke dielectric must be utilized in the manufacture of high-performance integrated circuits.
To meet the foregoing criterion, copper interconnect lines within a low-Ke dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most suitable interconnect structure. See xe2x80x9cCopper Goes Mainstream: Low-k to Followxe2x80x9d, Semiconductor International, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 xcexcxcexa9cm.; resistivities of aluminum-alloy films are in the range of 3.0 to 3.5 xcexcxcexa9cm.
Despite the advantageous properties of copper, it has not been as widely used as an interconnect material as one would expect. This is due, at least in part, to the difficulty of depositing copper metallization and, further, due to the need for the presence of barrier layer materials. The need for a barrier layer arises from the tendency of copper to diffuse into silicon junctions and alter the electrical characteristics of the semiconductor devices formed in the substrate. Barrier layers made of, for example, titanium nitride, tantalum nitride, etc., must be laid over the silicon junctions and any intervening layers prior to depositing a layer of copper to prevent such diffusion.
A number of processes for applying copper metallization to semiconductor workpieces have been developed in recent years. One such process is chemical vapor deposition (CVD), in which a thin copper film is formed on the surface of the barrier layer by thermal decomposition and/or reaction of gas phase copper compositions. A CVD process can result in conformal copper coverage over a variety of topological profiles, but such processes are expensive when used to implement an entire metallization layer.
Another known technique, physical vapor deposition (PVD), can readily deposit copper on the barrier layer with relatively good adhesion when compared to CVD processes. One disadvantage of PVD processes, however, is that they result in poor (non-conformal) step coverage when used to fill microstructures, such as vias and trenches, disposed in the surface of the semiconductor workpiece. For example, such non-conformal coverage results in less copper deposition at the bottom and especially on the sidewalls of trenches in the semiconductor devices.
Inadequate deposition of a PVD copper layer into a trench to form an interconnect line in the plane of a metallization layer is illustrated in FIG. 1. As illustrated, the upper portion of the trench is effectively xe2x80x9cpinched offxe2x80x9d before an adequate amount of copper has been deposited within the lower portions of the trench. This result in an open void region that seriously impacts the ability of the metallization line to carry the electrical signals for which it was designed.
Electrochemical deposition of copper has been found to provide the most cost-effective manner in which to deposit a copper metallization layer. In addition to being economically viable, such deposition techniques provide substantially conformal copper films that are mechanically and electrically suitable for interconnect structures. These techniques, however, are generally only suitable for applying copper to an electrically conductive layer. As such, an underlying conductive seed layer is generally applied to the workpiece before it is subject to an electrochemical deposition process. Techniques for electrodeposition of copper on a barrier layer material have not heretofore been commercially viable.
The present inventors have recognized that there exists a need to provide copper metallization processing techniques that 1) provide conformal copper coverage with adequate adhesion to the barrier layer, 2) provide adequate deposition speeds, and 3) are commercially viable. These needs are met by the apparatus and processes of the present invention as described below.
The present invention provides processes and apparatus for enhancing or repairing ultra-thin or incomplete metal seed layers that have been deposited on a workpiece, using electrolytic or electroless plating baths, in an electrodeposition reactor that is designed and adaptable for substrates having differing electrical properties.
One embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrochemically depositing additional metal on the ultra-thin metal seed layer within a principal fluid chamber of a reactor to provide an enhanced seed layer using a second deposition process. The second deposition process, which is different from the first deposition process, entails supplying electroplating power to a plurality of concentric anodes disposed at different positions within the principal fluid flow chamber relative to the workpiece. After seed layer repair, additional metal is deposited in an electrolytic bulk plating process onto the enhanced seed layer, under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrochemically depositing additional metal on the ultra-thin metal seed layer within a principal fluid chamber of a reactor to provide an enhanced seed layer using a second deposition process, that is different from the first deposition process. The second deposition process entails supplying electroplating power to a plurality of electrodes within the principal fluid flow chamber. At least two of the plurality of electrodes are independently connected to an electrical power supply. The supply of electrical power to the at least two electrodes is independently controlled during repair of the ultra-thin metal seed layer. After repair of the seed layer, additional metal is electrolytically deposited on the enhanced seed layer under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails subjecting the workpiece to an electrochemical deposition process that is different from the first deposition process, in an alkaline electroplating bath. The alkaline electroplating bath includes metal ions complexed with a complexing agent such that additional metal is deposited on the ultra-thin copper seed layer to thereby repair the seed layer. This results in an enhanced seed layer. The second deposition process is carried out by supplying electroplating power to a plurality of concentric anodes disposed at different positions, relative to the workpiece, within a principal fluid flow chamber of a reactor. Thereafter, additional metal is deposited on the enhanced seed layer using an electrolytic bulk deposition process under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails subjecting the workpiece to an electrochemical deposition process that is different from the first deposition process, in an alkaline electroplating bath. The bath includes metal ions complexed with a complexing agent such that additional metal is deposited on the ultra-thin copper seed layer to thereby repair the seed layer, resulting in an enhanced seed layer. The first deposition process entails supplying electroplating power to a plurality of electrodes within the principal fluid flow chamber, wherein at least two of the plurality of electrodes are independently connected to an electrical power supply. The supply of electrical power to the at least two electrodes is independently controlled during repair of the ultra-thin metal seed layer. Thereafter additional metal is electrolytically deposited on the enhanced seed layer under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrochemically depositing additional metal on the ultra-thin metal seed layer within a principal fluid chamber of a reactor to provide an enhanced seed layer using a second deposition process, that is different from the first deposition process. During repair, the workpiece is exposed to an electroplating solution within a fluid flow chamber of a reactor. The fluid flow chamber defines a sidewall and a plurality of nozzles disposed in the sidewall and arranged and directed to provide vertical and radial fluid flow components that combine to create a substantially uniform normal flow component radially across a surface of the workpiece on which the ultra-thin metal seed layer is formed. Thereafter, additional metal is electrolytically deposited on the enhanced seed layer under conditions in which the deposition rate of the deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails subjecting the workpiece to an electrochemical deposition process that is different from the first deposition process, in an alkaline electroplating bath. The bath includes metal ions complexed with a complexing agent such that additional metal is deposited on the ultra-thin copper seed layer to thereby repair the seed layer, resulting in an enhanced seed layer. During repair, the workpiece is exposed to an electroplating solution within a fluid flow chamber of a reactor, the fluid flow chamber defining a sidewall and a plurality of nozzles disposed in the sidewall and arranged and directed to provide vertical and radial fluid flow components that combine to create a substantially uniform normal flow component radially across a surface of the workpiece on which the ultra-thin metal seed layer is formed. Thereafter, additional metal is deposited on the enhanced seed layer under electrolytic plating conditions in which the deposition rate of the deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition, process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrochemically depositing additional metal on the ultra-thin metal seed layer within a principal fluid chamber of a reactor to provide an enhanced seed layer using a second electrolytic or electroless deposition process, that is different from the first deposition process. Thereafter, additional metal is electrolytically deposited in bulk on the enhanced seed layer under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer. The bulk deposition process entails supplying electroplating power to a plurality of concentric anodes disposed at different positions within the principal fluid flow chamber relative to the workpiece.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrolytically or electrolessly depositing additional metal on the ultra-thin metal seed layer to provide an enhanced seed layer using a second deposition process, that is different from the first deposition process. Thereafter, additional metal is electrolytically bulk deposited on the enhanced seed layer within a principal fluid chamber of a reactor under conditions in which the deposition rate of the electrolytic deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer. The bulk deposition entails supplying electroplating power to a plurality of electrodes within the principal fluid flow chamber, wherein at least two of the plurality of electrodes are independently connected to an electrical power supply. The supply of electrical power to the at least two electrodes is independently controlled during deposition.
Another embodiment of the invention provides a process for applying a metallization interconnect structure to a workpiece on which an ultra-thin metal seed layer has been formed using a first deposition process. The first deposition process anchors the ultra-thin metal seed layer to an underlying layer, the ultra-thin metal seed layer having physical characteristics that render it generally unsuitable for bulk electrolytic deposition of a metal onto the metal seed layer. The process entails repairing the ultra-thin metal seed layer by electrochemically depositing additional metal on the ultra-thin metal seed layer to provide an enhanced seed layer using a second deposition process, that is different from the first deposition process. Thereafter, additional metal is electrochemically bulk deposited on the enhanced seed layer within a principal fluid chamber of a reactor under conditions in which the deposition rate of the deposition process is substantially greater than the deposition rate of the process used to repair the metal seed layer. The bulk deposition entails exposing the workpiece to an electroplating solution within a fluid flow chamber of a reactor, the fluid flow chamber defining a sidewall and a plurality of nozzles disposed in the sidewall and arranged and directed to provide vertical and radial fluid flow components that combine to create a substantially uniform normal flow component radially across a surface of the workpiece on which the ultra-thin metal seed layer is formed.
The present invention employs a novel approach to the metallization of a workpiece, such as a semiconductor workpiece. In accordance with the invention, an alkaline electroplating bath is suitably used to electroplate metal onto a seed layer, electroplate metal directly onto a barrier layer material, or repair (i.e., enhance) an ultra-thin copper seed layer which has been deposited on the barrier layer using a deposition process such as PVD or CVD. The metal deposition in the alkaline bath suitably takes place in a reactor including a plurality of electrodes. In a first embodiment the electrodes are concentric annular anodes arranged at differing positions relative to the workpiece. In a second embodiment, the plurality of electrodes are independently controlled for greater uniformity in metal deposition across the workpiece. In a third embodiment, the reactor is configured to induce a helical flow pattern in the plating bath solution during deposition.
The resulting metal layer provides an excellent conformal copper coating that fills trenches, vias, and other microstructures in the workpiece. When used for seed layer enhancement, the resulting metal seed layer provides an excellent conformal metal coating that allows the microstructures to be filled with a copper layer having good uniformity using electrochemical deposition techniques. Further, metal layers that are electroplated in the disclosed manner exhibit low sheet resistance and are readily annealed at low temperatures.
The disclosed process, as noted above, is applicable to a wide range of steps used in the manufacture of a metallization layer in a workpiece. The workpiece may, for example, be a semiconductor workpiece that is processed to form integrated circuits or other microelectronic components, or a micromechanical device. Without limitation as to the applicability of the disclosed invention, a process for enhancing a seed layer is described.
A process for applying a metallization interconnect structure to a workpiece having a barrier layer deposited on a surface thereof is also set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer has a thickness of less than or equal to about 500 Angstroms and may be formed from any material that can serve as a seed layer for subsequent metal deposition. Such metals include, for example, copper, copper alloys, aluminum, aluminum alloys, nickel, nickel alloys, zinc, chromium, tin, gold, silver, lead, cadmium, platinum, palladium, iridium and ruthenium, etc. The ultra-thin seed layer is then enhanced or repaired by depositing additional metal thereon in a separate deposition step to provide an enhanced seed layer that is suitable for use in a primary metal deposition. The metal deposition in the alkaline bath suitably takes place in a reactor including a plurality of electrodes. In a first embodiment the electrodes are concentric annular anodes arranged at differing positions relative to the workpiece. In a second embodiment, the plurality of electrodes are independently controlled for greater uniformity in metal deposition across the workpiece. In a third embodiment, the reactor is configured to induce a helical flow pattern in the plating bath solution during deposition. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
In accordance with a specific embodiment of the process, a copper-containing metallization interconnect structure is formed. To this end, the ultra-thin seed layer is enhanced or repaired by subjecting the semiconductor workpiece to an electrochemical copper deposition process in which an alkaline bath having a complexing agent is employed. The copper complexing agent may be at least one complexing agent selected from a group consisting of EDTA, ED, and a polycarboxylic acid such as citric acid or salts thereof.
In an alternate embodiment, the seed layer may be enhanced by using an electroless plating bath composition, such as an electroless copper sulfuric acid bath.